VLSI Based Projects

IEEE TRANSACTIONS

 

S.NO

TITLE

YEAR

CATAGORY

1

Fast Radix-10 Multiplication Using Redundant BCD Codes

2014

Vhdl/verilog

2

Recursive Approach to the Design of a Parallel Self-Timed Adder

2014

Vhdl/verilog

3

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

2014

Vhdl/verilog

4

Area–Delay–Power Efficient Carry-Select Adder

2014

Vhdl/verilog

5

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits

2014

Lp vlsi

6

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme

2014

Lp vlsi

7

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

2014

Lp vlsi

8

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

2014

Lp vlsi

9

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

2014

Vhdl/verilog

10

Area-Delay Efficient Binary Adders in QCA

2014

Lp vlsi

11

Reviewing High-Radix Signed-Digit Adders

2014

Vhdl/verilog

12

Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

2014

Vhdl/verilog

13

A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flop

2014

Vhdl/verilog

14

A 65 nm Cryptographic Processor for High Speed Pairing Computation

2014

Vhdl/verilog

15

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path

2014

Lp vlsi

16

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

2014

Lp vlsi

17

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

2014

Vhdl/verilog

18

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

2014

Vhdl/verilog

19

FPGA Implementation of an Efficient Algorithm for the Calculation of Charged Particle Trajectories in Cosmic Ray Detectors

2014

Vhdl/verilog

20

Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes

2013

Vhdl/verilog

21

Multioperand Redundant Adders on FPGAs

2013

Vhdl/verilog

22

Design of high speed hybrid carry select adder

2012

Vhdl/verilog

23

Accumulator Based 3-Weight Pattern Generation

2012

Vhdl/verilog

24

Low-Power and Area-Efficient Carry Select Adder

2012

Vhdl/verilog

25

Accumulator Based 3-Weight Pattern Generation

2011

Vhdl/verilog

26

Area Optimized Low Power Arithmetic And Logic Unit

2011

Lp vlsi

 

 

 

 

 

IEEE CONFERENCES

 

 

 

 

1

Realization of 2:4 reversible decoder and its applications

2014

Lp vlsi

2

Design and Estimation of delay, power and area for Parallel prefix adders

2014

Vhdl/verilog

3

Low power Square and Cube Architectures

Using Vedic Sutras

2014

Vhdl/verilog

4

All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer

2014

Vhdl/verilog

5

Design of Dedicated Reversible Quantum Circuitry for Square Computation

2014

Vhdl/verilog

6

An Optimized Design of Reversible Quantum Comparator

2014

Lp vlsi

7

Residue Arithmetic’s using Reversible Logic Gates

2014

Vhdl/verilog

8

Implementation Of Floating Point Mac Using Residue Number System

2014

Vhdl/verilog

9

Binary Division Algorithm and High Speed Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics)

2014

Vhdl/verilog

10

Energy Efficient Code Converters using Reversible Logic Gates

2013

Vhdl/verilog

11

A High Speed Binary Floating Point Multiplier Using Dadda Algorithm

2013

Vhdl/verilog

12

A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor

2013

Lp vlsi

13

Optimized Reversible Vedic Multipliers for High Speed Low Power Operations

2013

Vhdl/verilog

14

Energy Efficient Code Converters using Reversible Logic Gates

2013

Vhdl/verilog

15

Design of Low Logical Cost Conservative Reversible Adders using Novel PCTG

2013

Vhdl/verilog

16

Contemplation of  Synchronous Gray Code Counter and its Variants using Reversible Logic Gates

2013

Vhdl/verilog

17

ACHIEVEING REDUCED AREA BY  MULTI-BIT FLIP FLOP DESIGN

2013

Vhdl/verilog

18

Design of Low Power Comparator Circuit  Based on Reversible Logic Technology

2013

Vhdl/verilog

19

Design ofHigh Performance 64 bit MAC Unit

2013

Vhdl/verilog

20

Novel High Speed Vedic Mathematics Multiplier using Compressors

2013

Vhdl/verilog

21

VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog

2013

Vhdl/verilog

22

Application of the DLFSR Generators in Spread Spectrum Communication 

2012

Vhdl/verilog

23

Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation

2012

Vhdl/verilog

24

USB Receiver/Transmitter for FPGA Implementation

2012

Vhdl/verilog

25

Design and Implementation of Floating Point Multiplier based on Vedic Multiplication Technique

2012

Vhdl/verilog

26

How the CRC algorithm in Xmodem protocol implementation in FPGA

2012

Vhdl/verilog

27

High speed Modified Booth Encoder multiplier for signed and unsigned numbers

2012

Vhdl/verilog

 

  1.  

  1.  

  1.  

  1.  

  1. 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler

  2. A 16-Core Processor With Shared-Memory and

  3. An Optimized Modified Booth Recoder for Efficient

  4. High-Throughput Multistandard Transform

  5. Improved 8-Point Approximate DCT

  6. Area–Delay–Power Efficient Carry-Select Adder

  7. Multifunction Residue Architectures

  8. Area-Delay-Power Efficient Fixed-Point LMS

  9. Aging-Aware Reliable Multiplier Design With

  10. Fast Sign Detection Algorithm for the RNS Module

  11. Efficient Integer DCT Architectures for HEVC

  12. Bit-Level Optimization of Adder-Trees

  13. Design of Efficient Binary Comparators

  14. Reverse Converter Design via Parallel-Prefix Adders

  15. Low-Complexity Low-Latency Architecture for Matching

  16.   VLSI Verilog Projects 2013

  17.  

  18. Energy-Efficient High-Throughput Montgomery

  19. Error Detection in Majority Logic Decoding of Euclidean

  20. Low-Power, High-Throughput, and Low-Area

  21. Pipelined Radix- Feedforward FFT Architectures

  22. A Single-Channel Architecture for Algebraic

  23. Radix-4 and Radix-8 Booth

  24. High-Performance Hardware

  25. pipelined  Radix 2K Feed forward

  26. Design and Implementation On-Chip Permutation Network for Multiprocessor System-On-Chip

  27. Multioperand Redundant Adders on FPGAs

  28. Global Built-In Self-Repair for 3D Memories with

  29. A Practical NoC Design for Parallel DES Computation

  30. Parallel AES Encryption Engines

  31. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog

  32. A VLIW architecture for executing multi-scalarvector instructions on unified datapath

  33. A Novel Modulo Adder for

  34. Low-Cost FIR Filter Designs Based on Faithfully

  35. Low-Power, High-Throughput, and Low-Area

  36. Efficient VLSI Architectures of Split-Radix FFT

  37. A Design Technique for Faster Dadda Multiplier

  38. Low-Power, High-Throughput, and Low-Area

  39. BIST Based Test Applications Enhanced with Adaptive Low Power RTPG

  40. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA

  41. Enhanced Area Efficient Architecture for 128 bit Modified CSLA

  42. High Performance Hardware Implementation

  43. High Performance Pipelined Design for FFT

  44. Implementation of I2C Master Bus Controller

  45. Novel High Speed Vedic Mathematics Multiplier

  46. Period Extension and Randomness Enhancement Using

  47. VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog

  48. VLSI implementation of Fast Addition using

  49. FPGA architecture for OFDM software defined radio with an optimized direct digital frequeney syntherizer

  50. Implementation of UART with BIST Technique in

  51. A High Speed Binary Floating Point Multiplier Using Dadda Algorithm

  52. Soft-Error-Resilient FPGAs Using 2D hamming code

  53. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

  54. Efficient Majority Logic Fault Detection With

  55. Product code scheney for error correction in mlc nand flash memorles

  56. Scalable Digital CMOS Comparator

  57. Low-Power and Area-Efficient Carry Select Adder

  58. A Nonbinary LDPC Decoder Architecture With Ad

  59. Low-Cost Binary128 Floating-Point FMA Unit

  60. Efficient Majority Logic Fault Detection With

  61. Viterbi-Based Efficient Test Data

  62. Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA

  63. Design and FPGA-based Implementation of a High Performance 32-bit DSP Processor

  64. FPGA Implementation of Sine and Cosine Generators using CORDIC Algorithm

  65. Reconfigurable Routers for  low_power_high_performance_routers

  66. Configurable Multimode floating point units

  67. data encoding scheme in noc

  68. A New VLSI Architecture of Parallel Multiplier A

  69. FPGA Implementation of Network on Chip

  70. Design and  Implementation  of  Multi-mode QC­